Variable impedance network for an integrated circuit potentiometer

ABSTRACT

An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance elements is connected in series in a mirrored configuration about the center impedance element.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part of co-pending U.S.patent application Ser. No. 09/989,874, filed Nov. 20, 2001 and entitled“Variable Impedance Network for an Integrated Circuit” and commonlyassigned to the assignee of the present invention.

BACKGROUND

[0002] The present invention relates to variable impedance networks.More particularly, the invention relates to such variable impedancenetworks for an integrated circuit potentiometer.

[0003] Variable impedance networks are usually manually adjusted toprovide a selected impedance so as to affect some aspect of the circuitin which the networks are located. These variable impedance networks areusually in the form of variable resistors, also called potentiometers.However, circuits using variable inductors or capacitors may also beformed.

[0004] Manual adjustment of potentiometers is usually undesirable incircuits under the control of data processing systems or other externalelectric circuits where ongoing adjustment of the potentiometer isnecessary for circuit operation. The data processing system often mustchange the value of the variable impedance network in a time that isshort relative to the time required to complete a manual adjustment ofthe variable impedance element. Therefore, special purpose integratedcircuit variable impedance networks have been employed in the prior art.These networks allow the level of attenuation to be adjusted under thedigital control of an external data processing system.

[0005] For example, Tanaka, et al., U.S. Pat. No. 4,468,607, teaches aladder attenuator which is controlled by a binary number by means of aswitch circuit. Depending on the stage of the switches in this switchcircuit, one or more stages of attenuation are introduced into thesignal path. However, teachings of Tanaka may require a large number offixed impedance elements and switches for a large range of impedances.Accordingly, Drori, et al., U.S. Pat. No. 5,084,667, suggests a numberof embodiments of variable impedance elements which minimizes the numberof separate resistors required to achieve the equivalent resolutionachievable using a series arrangement of resistors.

SUMMARY

[0006] The present invention, in one aspect, describes an impedancenetwork, which includes at least one end terminal, a wiper terminal, acenter impedance element, and a first plurality of impedance elements.The wiper terminal provides a tap position at a selected impedance valueof the impedance network, selectable at a specified increment value. Thefirst plurality of impedance elements is configured to reduce resistancevariation during switching from one tap position to another tapposition. The first plurality of impedance elements is connected inseries in a mirrored configuration about the center impedance element.

[0007] In another aspect, the present invention describes a method forconfiguring an impedance network. The method includes first configuringa first plurality of resistors selectively connectable in parallel, andconnecting a second plurality of resistive elements in series, whereeach resistive element includes equivalent resistance formed by thefirst plurality of resistors. A center resistor is provided, and thesecond plurality of resistive elements is configured into a mirroredconfiguration with respect to the center resistor. Nodes of the secondplurality of resistive elements are then selectively connected to awiper terminal of the impedance network.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1A shows a conventional variable resistance network.

[0009]FIG. 1B shows a standard center-tapped potentiometer.

[0010]FIG. 2 illustrates an impedance network array configuration.

[0011]FIG. 3 illustrates a resistor network configuration for 64-tappotentiometer.

[0012]FIG. 4 illustrates a three terminal potentiometer implemented witha variable resistive network in accordance with an embodiment of theinvention.

[0013]FIG. 5 is a graph comparing wiper/pass transistors used by theconventional approach to the improved approach.

[0014]FIG. 6 shows a schematic representation of the 256-tapserial/binary-based network in accordance with an embodiment of theinvention.

[0015]FIG. 7A shows one implementation of the trim option circuit.

[0016]FIG. 7B shows one implementation of a resistive network withoutthe trimming circuit.

[0017]FIG. 8A shows the binary-based resistor network with a trimmingcircuit.

[0018]FIG. 8B shows a serial/binary-based resistor network with atrimming circuit.

DETAILED DESCRIPTION

[0019] In recognition of the above-stated challenges associated withprior art designs of variable impedance networks, alternativeembodiments for a variable impedance network which reduces overheadcircuits including wiper transistors are described. Consequently, forpurposes of illustration and not for purposes of limitation, theexemplary embodiments of the invention are described in a mannerconsistent with such use, though clearly the invention is not solimited.

[0020] A conventional variable resistance network 100 is illustrated inFIG. 1A. The network 100 includes a counter 102, a control circuitry104, a decoder 106, and a network array 108 having a transistor array110 and a resistor array 112. In the illustrated example, the networkarray 108 has three terminals, H, L and W. Hence, the network array 108simulates a standard potentiometer 120, such as the one shown in FIG.1B. Terminals H and L correspond to the end terminals, while terminal Wcorresponds to the center tap of the potentiometer 120.

[0021] In the illustrated example of FIG. 1A, the resistor array 112includes 32 equal resistor elements (R) arranged in series to represent32 tap positions at the wiper nodes of the potentiometer 120. However,any number of resistor elements may be used to provide smaller or largerresistance value than this example. The transistor array 110 includeswiper transistors that are used to connect various combinations ofresistor elements between two terminals H and W.

[0022] The particular combination is determined by a value stored in acounter 102, which may be altered by two signals, U/D and INCR. The U/Dsignal determines whether the counter 102 will be incremented ordecremented by a predetermined amount in response to the increment(INCR) signal. This value is coupled to a 1-of-N decoder 106, whereN=32. The output of this decoder 106 controls the plurality of wipertransistors in the transistor array 110. Since N is the maximum valuewhich may be stored in the counter 102, there are N nodes in theresistor array 112, each node corresponding to a given counter value.Each node may be coupled to terminal W by applying a signal to thecorresponding wiper transistor in the transistor array 110.

[0023] The value stored in the counter 102 may be transferred to amemory in the control circuitry 104 in response to specified voltagetransitions on a chip select (CS) line. The chip select line alsoenables the counter 102. When the chip select line is low, the counter102 responds to signals on U/D and INCR lines. This enables the circuitcontrolling the variable resistance network 100 to alter the valuestored in counter 102.

[0024] The control circuitry 104 also monitors supply voltages (V_(cc)and V_(ss)) to load the value stored in the memory into the counter 102when power is applied to the variable resistance network 100. Thisensures that the last value stored in counter 102 before power wasremoved from the variable resistance network 100 will be restored whenthe power is once again applied to the variable resistance network 100.

[0025] With the above-described approach illustrated in FIGS. 1A and 1B,N wiper transistors are required to generate N tap positions. Hence,when N becomes large (e.g., N>100), the area of the die occupied by thewiper transistors may significantly increase, especially when thespecification for wiper resistance is low (i.e., 50 ohms or less).

[0026] Accordingly, the present embodiments include solutions to theabove-stated undesirable outcome of large N by providing a variableimpedance network which requires fewer wiper transistors. Moreover, theteachings of these embodiments may be extended to include impedancenetworks having elements other than resistors, such as capacitors orinductors. In the below-described embodiments, the impedance network isa binary numbering scheme assigned to a plurality of serially connectedresistive pairs, where each pair is connected in parallel. However, inan alternative embodiment, more than two resistors may be configured inparallel arrangement to provide wider range of resistance values, andthus, further reduce the wiper transistor count. In a furtherembodiment, bypass transistors may be provided to bypass certainresistors. This may also provide wider range resistance values.

[0027] An impedance network array configuration 200 is illustrated inFIG. 2, in which the network array 200 is configured into a plurality ofserially connected resistor pairs, where each pair is connected inparallel. Furthermore, the plurality of serially connected resistorpairs is connected with connection nodes. Resistance values of theresistor pair connected in parallel are equal. A switching element, suchas a transistor, may be connected in series with one resistor of theresistive pair to either provide that resistor in parallel or todisconnect that resistor. In particular, the transistor may be afield-effect transistor (FET). Resistance values of the plurality ofserially connected resistor pairs may be different. In this example, theresistance values of the plurality of serially connected resistor pairsare mirrored with respect to the center node, O. However, the mirroredconfiguration is not required. Furthermore, each resistor pair isselectively connected to the wiper terminal (W) through a switchingelement such as a transistor to select different combinations of seriesresistances. In particular, the transistor may be a field-effecttransistor (FET).

[0028] Further, the impedance network array configuration 200 isarranged to meet two constraints. The first constraint is to keep theend-to-end resistance of the array (i.e., potentiometer) 200 constant.This constraint for constant end-to-end resistance between the endterminals H and L must be followed to ensure proper functioning of thepotentiometer. The second constraint is to generate all possible taps atthe variable node of the potentiometer, with each tap providing a unitresistance (R). Therefore, a 21R end-to-end resistance potentiometerwith 22 1R taps may be configured as shown in FIG. 2.

[0029] To accomplish the first constraint, the binary sequence ismirrored around the center node O so that any resistance between H and Wis complemented with a resistance between W and L that keeps theend-to-end resistance constant to 21R. For example, if 1R (i.e., 2R∥2R,where ∥ indicates parallel configuration) is selected on the H-to-W sideby turning on transistors T1 and T_(w) 2, a 20R resistance must beselected with the rest of the resistor array on the W-to-L side byturning on T2 and T3. This generates a 20R configured by(4R∥4R)+(8R∥8R)+8R+4R+2R=2R+4R+8R+4R+2R. In the illustrated embodiment,transistors labeled TX, where X is between 1 and 6, are referred to aspass transistors. Transistors labeled as T_(w)X, where X is between 1and 7, are referred to as wiper transistors. Thus, the pass transistorallows resistors into parallel configuration, while the wiper transistorallows incorporation of each series resistance to be applied.

[0030] The second constraint to achieve all minimum increment (R) tapsmay be ensured by determining the end-to-end resistance using thefollowing formula:

R _(end-to-end) =R _(max) +R _(min),

[0031] where R_(max) is the maximum resistance that may be configured upto the center (labeled as O in FIG. 2) of the network array 200 (i.e.,configured with one-half of the network array); and R_(min) is theminimum resistance that may be configured up to the center (labeled as Oin FIG. 2) of the network array 200.

[0032] In FIG. 2, R_(max) is 14R and R_(min) is 7R. Hence, in thisconfiguration, R_(min)=R_(max)/2. Furthermore,R_(end-to-end)=14R+7R=21R. This end-to-end resistance satisfies the twoconstraints and generates all the possible 22 taps for the 21Rpotentiometer 200. Accordingly, 1R is achieved, for example, on theH-to-W side by turning on transistors T1 and T_(w) 2. This requires 20Ron the rest of the network array on the W-to-L side by turning ontransistors T2 and T3. 2R is achieved on the H-to-W side by turning ontransistor T_(w) 2. This requires 19R on the rest of the network arrayon the W-to-L side by turning on transistors T2, T3, and T6.Furthermore, 3R is achieved on the H-to-W side by turning on transistorsT1, T2, and T_(w) 3. This requires 18R on the rest of the network arrayon the W-to-L side by turning on T3. Similar arrangements may beconfigured to provide the rest of the resistance values from 4R to 21R,at an increment of 1R.

[0033] Table 1 shows resistor network configurations for 64, 128, and256 tap potentiometer configurations, and their resistance constructionvalues and sequence. Although the table shows only three configurations,further configurations with any number of steps may be arrangedsimilarly. As an example, FIG. 3 illustrates a resistor networkconfiguration 300 for 64-tap potentiometer. TABLE 1 Total Step R_(TOTAL)R_(MIN) R_(MAX) Network Configuration 64  63R 21R 42R 2R, 4R, 8R, 16R,12R, 12R, 16R, 8R, 4R, 2R 128 127R 41R 86R 2R, 4R, 8R, 16R, 32R, 24R,24R, 32R, 16R, 8R, 4R, 2R 256 255R 85R 170R  2R, 4R, 8R, 16R, 32R, 64R,44R, 44R, 64R, 32R, 16R, 8R, 4R, 2R

[0034]FIG. 4 illustrates a three terminal potentiometer implemented witha variable resistive network 400 in accordance with an embodiment of theinvention. However, the network 400 may be implemented with anyimpedance elements. The network 400 has been configured to overcome someof the difficulties presented in the networks 200, 300 of FIGS. 2 and 3,and tabulated in Table 1.

[0035] In the illustrated embodiment, the network 400 is configured withresistor elements connected in parallel and in series depending on thecontrols to the switches. Furthermore, these resistor element values arechosen such that it compliments a binary numbering scheme. Hence, theimproved binary-based resistor network 400 was designed with two goalsin mind: to create an easily expandable resistor network pattern thatallows for equal step increments of 32, 64, 128, 256, etc; and hassimple decoding scheme.

[0036] The illustrated resistor network 400 includes a pair of 1Rresistors before parallel combinations of 2R, 4R, 8R, etc., at the twoend terminals. The network also includes a single resistor element inthe middle of the network. This resistor element is chosen based on thenumber of resistor steps desired. Moreover, the network 400 is designedin such a way that the second half 404 of the network 400 is a mirroredversion of the first half 402 (i.e., 1R-2R-4R-8R in the first half and8R-4R-2R-1R in the second half). Hence, the total resistance of thisnetwork 400 is 1R+2R+4R+8R+8R+(8R+4R+2R)/2+1R=31R, which creates 32resistor steps. This mirrored configuration may be extended to anynumber of binary configurations.

[0037] Further, the mirrored configurations of the network 400 enablesthe controls of the pass gate switches, R[x], to be created by theinverse of the input bits (for the first half 402 of the network 400),and the input bits themselves (for the second half 404 of the network400). Because the resistor controls to the two halves 402, 404 of thenetwork 400 are mutually exclusive, the network 400 almost always sees acombination of one resistance (2R+4R+8R) and a parallel combination ofthat resistance (2R/2+4R/2+8R/2). This keeps the total end-to-endresistance constant, regardless of which combinations of series andparallel resistors were used in the first half 402 of the network 400.

[0038] The controls for the first half 402 of the wiper switches, S[x],are determined by the first 1 in the most significant position of thedigital input. Controls for the second half 404 of the wiper switches,S[x], are determined by the first 0 in the most significant position ofthe digital input. Table 2 illustrates the implementation of thecontrols for the pass gate and wiper switches.

[0039] The illustrated network 400 has been described in terms ofconfiguration used for digital inputs of 5 bits to create 32 1Rresistance steps. However, the advantage is that the network 400 isreadily applicable to a digital input of any bit length, so long as thenecessary resistor components are added or subtracted. For example, if adigital input of 8 bits is to be used, the network may be expanded to1R(s), 2R, 4R, 8R, 16R, 32R, 64R, 64R(s), 64R, 32R, 16R, 8R, 4R, 2R,1R(s), where (s) indicates a single resistor. Hence, this configurationfollows the same pattern as the 32-step network. Table 3 illustratescircuit implementations of different number of resistor taps. Wiper andresistor switching controls for the new stages also follow the samepatterns as before but expanded to accommodate for 8 input bits. Noextra decoding logic needs to be developed and no patterns need to beestablished. TABLE 2 Wiper and Pass Gate controls for the improvedbinary-based network WIPER CONTROLS PASS GATE CONTROLS Decimal Binary S0S1 S2 S3 S4 S5 S6 S7 S8 S9 Binary R0 R1 R2 R3 R4 R5 0 00000 1 0 0 0 0 00 0 0 0 00000 0 0 0 1 1 1 1 00001 0 1 0 0 0 0 0 0 0 0 00001 1 0 0 1 1 02 00010 0 0 1 0 0 0 0 0 0 0 00010 0 1 0 1 0 1 3 00011 0 0 1 0 0 0 0 0 00 00011 1 1 0 1 0 0 4 00100 0 0 0 1 0 0 0 0 0 0 00100 0 0 1 0 1 1 500101 0 0 0 1 0 0 0 0 0 0 00101 1 0 1 0 1 0 6 00110 0 0 0 1 0 0 0 0 0 000110 0 1 1 0 0 1 7 00111 0 0 0 1 0 0 0 0 0 0 00111 1 1 1 0 0 0 8 010000 0 0 0 1 0 0 0 0 0 01000 0 0 0 1 1 1 9 01001 0 0 0 0 1 0 0 0 0 0 010011 0 0 1 1 0 10 01010 0 0 0 0 1 0 0 0 0 0 01010 0 1 0 1 0 1 11 01011 0 00 0 1 0 0 0 0 0 01011 1 1 0 1 0 0 12 01100 0 0 0 0 1 0 0 0 0 0 01100 0 01 0 1 1 13 01101 0 0 0 0 1 0 0 0 0 0 01101 1 0 1 0 1 0 14 01110 0 0 0 01 0 0 0 0 0 01110 0 1 1 0 0 1 15 01111 0 0 0 0 1 0 0 0 0 0 01111 1 1 1 00 0 16 10000 0 0 0 0 0 1 0 0 0 0 10000 0 0 0 1 1 1 17 10001 0 0 0 0 0 10 0 0 0 10001 1 0 0 1 1 0 18 10010 0 0 0 0 0 1 0 0 0 0 10010 0 1 0 1 0 119 10011 0 0 0 0 0 1 0 0 0 0 10011 1 1 0 1 0 0 20 10100 0 0 0 0 0 1 0 00 0 10100 0 0 1 0 1 1 21 10101 0 0 0 0 0 1 0 0 0 0 10101 1 0 1 0 1 0 2210110 0 0 0 0 0 1 0 0 0 0 10110 0 1 1 0 0 1 23 10111 0 0 0 0 0 1 0 0 0 010111 1 1 1 0 0 0 24 11000 0 0 0 0 0 0 1 0 0 0 11000 0 0 0 1 1 1 2511001 0 0 0 0 0 0 1 0 0 0 11001 1 0 0 1 1 0 26 11010 0 0 0 0 0 0 1 0 0 011010 0 1 0 1 0 1 27 11011 0 0 0 0 0 0 1 0 0 0 11011 1 1 0 1 0 0 2811100 0 0 0 0 0 0 0 1 0 0 11100 0 0 1 0 1 1 29 11101 0 0 0 0 0 0 0 1 0 011101 1 0 1 0 1 0 30 11110 0 0 0 0 0 0 0 0 1 0 11110 0 1 1 0 0 1 3111111 0 0 0 0 0 0 0 0 0 1 11111 1 1 1 0 0 0

[0040] TABLE 3 Resistor network implementations for various number oftap positions Resistor Network Design All elements represent a pair ofresistors, one with a pass- Resistor gate, one without Taps note: (s)designates only single resistor 32 1R(s), 2R, 4R, 8R, 8R(s), 8R, 4R, 2R,1R(s) 64 1R(s), 2R, 4R, 8R, 16R, 16R(s), 16R, 8R, 4R, 2R, 1R(s) 1281R(s), 2R, 4R, 8R, 16R, 32R, 32R(s), 32R, 16R, 8R, 4R, 2R, 1R(s) 2561R(s), 2R, 4R, 8R, 16R, 32R, 64R, 64R(s), 64R, 32R, 16R, 8R, 4R, 2R,1R(s) 512 1R(s), 2R, 4R, 8R, 16R, 32R, 64R, 128R, 128R(s), 128R, 64R,32R, 16R, 8R, 4R, 2R, 1R(s) 1024 1R(s), 2R, 4R, 8R, 16R, 32R, 64R, 128R,256R, 256R(s), 256R, 128R, 64R, 32R, 16R, 8R, 4R, 2R, 1R(s)

[0041] The improved binary-based network 400 still maintains theadvantages of the original binary-based network 200, 300, including thereduced parasitic capacitance and fewer number of wiper transferswitches. However, the improved network 400 provides further advantageby having fewer total unit resistors and total pass gates. Table 4 showsthe difference between the resources used by the conventional approach100, the original binary-based network approach 200, 300, and theimproved binary-based approach 400. FIG. 5 is a graph comparingwiper/pass transistors used by the conventional approach to the improvedapproach. TABLE 4 Element counts in the Conventional (C), OriginalBinary-based (O), and Improved Binary Based (I) approach total totalresistor unit wiper switching Resistor elements resistors elementselements Taps C O I C O I C O I C O I 32 31 N/A 15 31 N/A 66 32 N/A 1032 N/A 16 64 63 20 19 63 168 138 64 11 12 64 31 20 128 127 N/A 23 127N/A 282 128 N/A 14 128 N/A 24 256 255 28 27 255 680 570 256 15 16 256 4328 512 511 N/A 31 511 N/A 1146 512 N/A 18 512 N/A 32 1024 1023 36 351023 2728  2298 1024 19 20 1024 55 36

[0042] During switching from one tap to the other tap, the wipertransistors switch on and off based on the tap selection address. Duringthe wiper transistor switching (one turning on and the other turningoff), an overlap time is intentionally introduced to keep the outputimpedance of the wiper stable. Therefore, one difficulty faced by theimproved binary-based approach is that both wiper devices are turned onmomentarily. This essentially creates a short through part of theresistor network and the end-to-end total resistance of the network iseffectively reduced by the amount the wiper switches shorted out. In theoriginal binary-based network and the improved binary-based network, themaximum resistance reduction occurs across the 64R elements for a 256tap resistive network. This creates a 25% reduction in end-to-endresistance. However, such a high operational variation in end-to-endresistance is undesirable for a system where the end-to-end resistancetransiently changes during the tap position change. TABLE 5Serial/Binary (SB) based approach 256 tap design 1R(s), 2R, 4R, 8R, 16R,32R, 64R, 64R(s), 64R, 32R, 16R, 8R, 4R, 2R, 1R(s) 1R(s), 2R, 4R, 8R,16R, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16R, 8R, 4R,2R, 1R(s)

[0043] In a new network approach, referred to as a serial/binary-basedapproach, instead of having the middle 32R, 64R, 64R(s), 64R, 32Rstages, the middle stage is replaced with an equivalent string ofthirteen 16R resistors. Total end-to-end resistance still remains at255R. Table 5 shows the new configuration of the network. In thisembodiment, since the largest element in the network is 16R, shortingout that largest element results in roughly a 6% decrease in resistance,which a much more acceptable variation. This concept may be extended toany number of tap designs.

[0044]FIG. 6 shows a schematic representation of the 256-tapserial/binary-based network 600 in accordance with an embodiment of theinvention. This network 600 minimizes the transient end-to-endresistance change during the tap position switching condition.Furthermore, the amount of the change is proportional to the value ofthe largest resistor elements between wiper transistors. Hence, thisapproach 600 shares the advantages of the original binary, and improvedbinary approaches, but also reduces the resistor switches/pass devicesto improve the end-to-end resistance variation. Although theserial/binary approach 600 requires additional wiper transistorscompared to the strictly binary approach, this serial/binary approach600 requires less wiper transistors than the conventional approach. Forexample, by replacing the middle stages with a series of 16R resistors,the new network 600 requires 8 extra wiper switches. On the plus side,the new network 600 requires 4 less pass gate switches. Therefore thetotal difference is only 4 extra switch elements.

[0045] The network 600 uses pass gates switches to connect the binaryresistors. These pass gate switches have a parasitic resistance thatintroduces an error into the wiper node, and into the end-to-endresistance. This error may have adverse impact on the performanceparameters of the potentiometer such as Integral non-linearity (INL),and differential non-linearity (DNL). Hence, to minimize this error, atrimming network 700 may be implemented at the two ends of a resistancenetwork, such as the network 600.

[0046]FIG. 7A shows the implementation of the trim option circuit 700.The trimming network 700 generates resistance ranging from 0.5 to 4.0 R.By providing a nonvolatile memory that controls the pass gates, it ispossible to trim the potentiometer for every step and significantlyimprove the linearity of the resistance network. Table 6 shows thevalues of the trim circuit. TABLE 6 ideal actual 1 1.3607 1.25 1.71781.5 1.7679 1.75 2.125 2 2.194 2.2 2.4483 2.5 2.7245 3 3.0816 3.5 3.64294 4

[0047] The ideal column indicated the resistance values that may beobtained by ignoring any parasitic resistance from the pass gateswitches. The actual column indicates the resistance values that may beobtained by assuming that a pass gate switch has a 0.8R value. FIG. 7Bshows the network 700 without the trimming circuit.

[0048]FIGS. 8A and 8B show the binary-based resistor network with atrimming circuit, and the serial/binary-based resistor network with atrimming circuit, respectively.

[0049] While specific embodiments of the invention have been illustratedand described, such descriptions have been for purposes of illustrationonly and not by way of limitation. Accordingly, throughout this detaileddescription, for the purposes of explanation, numerous specific detailswere set forth in order to provide a thorough understanding of thepresent invention. It will be apparent, however, to one skilled in theart that the embodiments may be practiced without some of these specificdetails. In other instances, well-known structures and functions werenot described in elaborate detail in order to avoid obscuring thesubject matter of the present invention. Accordingly, the scope andspirit of the invention should be judged in terms of the claims whichfollow.

What is claimed is:
 1. An impedance network, comprising: at least oneend terminal; a wiper terminal providing a tap position at a selectedimpedance value of the impedance network, selectable at a specifiedincrement value, said wiper terminal selectable as an end terminal; acenter impedance element; and a first plurality of impedance elementsconfigured to provide a range of impedance values with less number ofwiper switching elements than for an impedance network with impedanceelements having a uniformly selected increment value, the firstplurality of impedance elements connected in series in a mirroredconfiguration about the center impedance element.
 2. The network ofclaim 1, further comprising: at least first and second end impedanceelements coupled between the at least one end terminal and the firstplurality of impedance elements.
 3. The network of claim 2, wherein thefirst and second end impedance elements are unit valued resistors. 4.The network of claim 1, wherein said first plurality of impedanceelements includes a plurality of connection nodes which enables saidfirst plurality of impedance elements to be connected in series.
 5. Thenetwork of claim 4, wherein said first plurality of impedance elementsincludes a first plurality of wiper switching elements to selectivelycouple said plurality of connection nodes to the wiper terminal.
 6. Thenetwork of claim 5, wherein said first plurality of wiper switchingelements includes a plurality of transistors.
 7. The network of claim 6,wherein on/off states of said plurality of transistors are in a mirroredconfiguration around the center impedance element.
 8. The network ofclaim 6, wherein said plurality of transistors includes a plurality offield-effect transistors (FET).
 9. The network of claim 1, wherein eachimpedance element of said first plurality of impedance elements includesa second plurality of impedance elements selectively connectable inparallel.
 10. The network of claim 9, further comprising: a secondplurality of switching elements configured to selectively connect saidsecond plurality of impedance elements in parallel.
 11. The network ofclaim 10, wherein said second plurality of switching elements includes aplurality of transistors.
 12. The network of claim 11, wherein saidplurality of transistors includes a plurality of field-effecttransistors (FET).
 13. The network of claim 10, wherein said secondplurality of impedance elements includes a pair of resistors of equalvalues, selectively connectable in parallel.
 14. The network of claim12, wherein said pair of resistors in different impedance elements ofsaid first plurality of impedance elements are of unequal values. 15.The network of claim 14, wherein the value of the center impedanceelement is of equal value to the value of the pair of resistors in saidsecond plurality of impedance elements on both sides of the centerimpedance element.
 16. The network of claim 1, wherein the centerimpedance element and appropriate number of impedance elements adjacentto the center impedance element are configured to reduce resistancevariation during switching from one tap position to another tapposition.
 17. The network of claim 16, wherein the center impedanceelement and appropriate number of impedance elements adjacent to thecenter impedance element are configured with at least two more impedanceelements than the appropriate number.
 18. The network of claim 17,wherein said at least two more impedance elements has impedance valueless than that of the center impedance element and adjacent impedanceelements, but with equal value.
 19. An impedance network, comprising: atleast one end terminal; a wiper terminal providing a tap position at aselected impedance value of the impedance network, selectable at aspecified increment value, said wiper terminal selectable as an endterminal; a center impedance element; and a first plurality of impedanceelements configured to reduce resistance variation during switching fromone tap position to another tap position, the first plurality ofimpedance elements connected in series in a mirrored configuration aboutthe center impedance element.
 20. The network of claim 19, wherein thecenter impedance element and appropriate number of impedance elementsadjacent to the center impedance element are configured with at leasttwo more impedance elements than the appropriate number.
 21. The networkof claim 20, wherein said at least two more impedance elements hasimpedance value less than that of the center impedance element andadjacent impedance elements, but with equal value.
 22. A resistancenetwork having end terminals and a wiper terminal, comprising: a firstset of switching elements; a first plurality of resistors selectivelyconnectable in parallel with said first set of switching elements toform an equivalent resistive element where values of said firstplurality of resistors are equal; a center resistor; a second pluralityof resistors connected in series in a mirrored configuration about thecenter impedance element, each resistor of said second plurality ofresistors including said equivalent resistive element, resistance valuesof different equivalent resistive elements in said second plurality ofresistors is in a binary configuration with two middle equivalentresistive elements having an equal value with the value of the centerresistor; and a second set of switching elements to couple nodes of saidsecond plurality of resistors to the wiper terminal.
 23. The network ofclaim 22, further comprising: at least first and second end resistorscoupled to the end terminals.
 24. The network of claim 23, wherein theat least first and second end resistors are unit-valued resistors. 25.The network of claim 22, wherein said first set of switching elementsincludes a plurality of transistors.
 26. The network of claim 25,wherein said plurality of transistors includes a plurality offield-effect transistors (FET).
 27. A method for configuring animpedance network, comprising: first configuring a first plurality ofresistors selectively connectable in parallel; connecting a secondplurality of resistive elements in series, where each resistive elementincludes equivalent resistance formed by the first plurality ofresistors; providing a center resistor; second configuring said secondplurality of resistive elements into a mirrored configuration withrespect to the center resistor; and selectively connecting nodes of saidsecond plurality of resistive elements to a wiper terminal of theimpedance network.
 28. The method of claim 27, further comprising:providing a pair of unit-sized resistors, one at each end of the secondplurality of resistive elements.
 29. The method of claim 27, whereinproviding the center resistor includes configuring the value of thecenter resistor that is of equal value to the resistance of said secondplurality of resistive elements on both sides of the center resistor.30. The method of claim 27, further comprising: selectively connectingsaid first plurality of resistors in parallel with a plurality ofswitching elements.
 31. The method of claim 27, wherein said firstconfiguring includes providing resistors of equal value.
 32. The methodof claim 27, wherein said second configuring includes providingresistors of different values to different resistive elements of thesecond plurality of resistive elements.